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smsc EMC1701 datasheet revision 1.2 (09-27-10) datasheet product features EMC1701 high-side current-sense and internal 1c temperature monitor general description the EMC1701 is a combination high-side current sensing device with precision temperature measurement. it measures the voltage developed across an external sense resistor to represent the high-side current of a battery or voltage regulator. the EMC1701 also measures the source voltage and uses these measured values to present a proportional power calculation. the EMC1701 contains additional bi-directional peak detection circuitry to flag instantaneous current spikes with programmable time duration and magnitude threshold. finally, the EMC1701 includes an internal diode channel for ambient temperature measurement. both current sensing and temperature monitoring include two tiers of protection: one that can be masked and causes the alert pin to be asserted, and the other that cannot be masked and causes the therm pin to be asserted. applications ? notebook and desktop computers ? industrial ? power management systems ? embedded applications features ? high-side current sensor ? bi-directional current measurement ? measures source voltage and indicates power ratio ? 1% current measurement accuracy ? integrated over 82ms to 2.6sec with 11-bit resolution ? 3v to 24v bus voltage range ? independent hardware set instantaneous current peak detector (EMC1701-1 only) ? software controls to program time duration and magnitude threshold ? power supply options ? bus or separately powered for low voltage operation ? wide temperature operating range: -40c to +85c ? internal temperature monitor ? 1c accuracy (-5c < t a < 85c) ? alert and therm outputs for temperature, voltage, and out-of-current limit reporting ? smbus 2.0 interface ? pin-selectable smbus address ? block read and write ? available in a 12-pin 4mm x 4mm qfn rohs compliant package (EMC1701-1) ? available in a 10-pin msop rohs compliant package (EMC1701-2) block diagram analog mux internal temp diode smbus slave protocol smclk smdata addr_sel sense+ sense- dur_sel* th_sel* peak detection voltage and temp registers configuration 11 - 15 bit adc 13 - 15 bit adc current registers current limits voltage and temp limits therm alert power register *EMC1701-1 only
reel size is 4,000 pieces this product meets the halogen maximum concentration values per iec61249-2-21 for rohs compliance and environmen tal information, please visit www.smsc.com/rohs ordering number package features EMC1701-1-kp-tr 12-pin 4mm x 4mm qfn (lead-free rohs compliant) internal diode, current sensor, hardware set peak detector EMC1701-2-aizl-tr 10-pin msop (lead-free rohs compliant) internal diode, current sensor high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 2 smsc EMC1701 datasheet 80 arkay drive, hauppauge, ny 11788 (631) 435-6000, fax (631) 273-3123 copyright ? 2010 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc produc ts are included as a means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and produc t descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this inform ation does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystems corporat ion (?smsc?). product names and company na mes are the trademarks of their respective holders. smsc disclaims and excludes any and all warrant ies, including without limi tation any and all implied warranties of merchantabil ity, fitness for a particular purpose, title, a nd against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indi rect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of wa rranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages. ordering information:
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 3 revision 1.2 (09-27-10) datasheet table of contents chapter 1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 chapter 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 smbus electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 chapter 3 communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 system management bus interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.1 smbus start bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.2 smbus address and rd / wr bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.3 smbus ack and nack bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.4 smbus stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.5 smbus time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.6 smbus and i 2 c compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 smbus protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.1 write byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.2 read byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.3 send byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.4 receive byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.5 block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.6 block read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.7 alert response address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 chapter 4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 source monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.1 current measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.2 voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 4.1.3 power calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1.4 current peak detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 vdd biasing options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4 alert output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4.1 alert pin interrupt mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4.2 alert pin comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.5 therm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.6 temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 chapter 5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 data read interlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2 block mode support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3 temperature data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.6 conversion rate register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.7 temperature limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.8 one-shot register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.9 tcrit limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.10 channel mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.11 consecutive alert register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.12 high limit status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.13 low limit status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 4 smsc EMC1701 datasheet 5.14 crit limit status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.15 voltage sampling configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.16 current sense sampling configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 5.17 peak detection configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.18 sense voltage registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.19 source voltage registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.20 power ratio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.21 v sense limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.22 source voltage limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.23 critical voltage limit registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.24 product features register (EMC1701-1 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.25 product id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.26 smsc id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.27 revision register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 chapter 6 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1 EMC1701-1 package drawing (12-pin qfn 4mm x 4mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.2 EMC1701-2 package drawing (10-pin msop ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3 EMC1701 package markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 chapter 7 datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 5 revision 1.2 (09-27-10) datasheet list of figures figure 1.1 EMC1701 pin diagram 12-pin qfn 4mm x 4mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 1.2 EMC1701 pin diagram 10-pin msop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3.1 smbus timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4.1 EMC1701 system diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4.2 peak detection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6.1 12-pin qfn 4mm x 4mm package drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 6.2 12-pin qfn 4mm x 4mm package dimensions and notes . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 6.3 12-pin qfn 4mm x 4mm pcb footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 6.1 10-pin msop package drawings (see note 6.1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 6.2 10-pin msop package dimensions and notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 6.3 10-pin msop pcb footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 6.1 EMC1701-1 package markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 6.2 EMC1701-2 package markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 6 smsc EMC1701 datasheet list of tables table 1.1 pin description for EMC1701 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 1.2 pin types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2.2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2.3 smbus electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3.1 addr_sel resistor setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3.2 protocol format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3.3 write byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3.4 read byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3.5 send byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3.6 receive byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3.7 block write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3.8 block read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3.9 alert response address protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4.1 th_sel resistor setting (EMC1701-1 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 4.2 dur_sel resistor setting (EMC1701-1 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 5.1 register set in hexadecimal order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5.2 temperature data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5.3 temperature data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5.4 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5.5 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 5.6 conversion rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5.7 conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5.8 temperature limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5.9 one-shot register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 5.10 tcrit limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 5.11 channel mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 5.12 consecutive alert register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5.13 consecutive alert / therm settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 5.14 high limit status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 5.15 low limit status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 5.16 crit limit status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5.17 voltage sampling configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5.18 voltage queue settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 5.19 voltage averaging settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 5.20 current sense sampling configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 5.21 sense queue settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5.22 current sense averaging settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5.23 current sensing sampling time sett ings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5.24 total sampling times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5.25 current sensing range (full scale range) settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5.26 peak detection configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5.27 peak_det_th[3:0] bit decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 5.28 peak_det_dur[3:0] bit decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 5.29 sense voltage registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 5.30 v sense data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 5.31 source voltage registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 5.32 power ratio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 5.33 v sense limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 5.34 source voltage limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 5.35 critical voltage limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 5.36 product features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 7 revision 1.2 (09-27-10) datasheet table 5.37 product id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 5.38 manufacturer id register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 5.39 revision register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 7.1 customer revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 8 smsc EMC1701 datasheet chapter 1 pin description figure 1.1 EMC1701 pin diagram 12-pin qfn 4mm x 4mm figure 1.2 EMC1701 pin diagram 10-pin msop 2 3 4 5 6 9 8 7 vdd smclk smdata 1 12 11 10 addr_sel sense+ sense- alert th_sel therm dur_sel n/c n/c gnd emc 1701-1 emc 1701-2 smdata smclk alert vdd therm gnd 1 2 3 4 5 10 9 8 7 6 addr_sel sense+ sense- n/c
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 9 revision 1.2 (09-27-10) datasheet the pin types are described in ta b l e 1 . 2 . all pins labeled with (5v) are 5v tolerant. all pins labeled with (24v) are 24v tolerant. table 1.1 pin description for EMC1701 pin number EMC1701-1 pin number EMC1701-2 pin name pin function pin type 1 5 vdd positive power supply voltage power (24v) 2 2 n/c not internally connected n/a 3 n/a n/c not internally connected n/a 4 6 addr_sel selects smbus address ai 58therm active low output - requires pull-up resistor od (5v) 6 9 alert active low output - requires pull-up resistor od (5v) 7 10 smdata smbus data input/output - requires external pull-up resistor diod (5v) 8 1 smclk smbus clock input - requires external pull- up resistor di (5v) 9 n/a dur_sel selects peak detector duration ai 10 n/a th_sel selects peak detector threshold ai 11 3 sense- negative current sense measurement point ai (24v) 12 4 sense+ positive current sens e measurement point ai (24v) bottom pad 7 gnd ground power table 1.2 pin types pin type description power this pin is used to supply power or ground to the device. ai analog input - this pin is used as an input for analog signals. od open drain digital output - this pin is used as a digital output. it is open drain and requires a pull-up resistor. this pin is 5v tolerant. di digital input - this pin is used for digital inputs. this pin is 5v tolerant. diod open drain digital input / output - this pin is bi-directional. it is open drain and requires a pull-up resistor. this pin is 5v tolerant.
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 10 smsc EMC1701 datasheet chapter 2 electrical characteristics note 2.1 stresses at or above those values listed could cause permanent damage to the device. this is a stress rating only, and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. prolonged stresses above the stated operating levels and below the absolute maximum ratings may degrade device performance and lead to permanent damage. note 2.2 all voltages are relative to ground. note 2.3 the package power dissipation specification assumes a thermal via design with the thermal landing be soldered to the pcb ground plane with four 12 mil vias (where applicable). note 2.4 junction to ambient ( ja ) is dependent on the design of t he thermal vias. without thermal vias and a thermal landing, the ja is approximately 60c/w (EMC1701-1) including localized pcb temp erature increase. table 2.1 absolute maximum ratings voltage on 5v tolerant pins -0.3 to 5.5 v voltage on 2v tolerant pins -0.3 to 2 v voltage on vdd, sense- and sense+ pins -0.3 to 26 v voltage on any other pin to gnd -0.3 to 4 v voltage between sense pins ( |(sense+ - sense-)| ) < 6 v package power dissipation 0.5w up to t a = 85c w junction to ambient ( ja ) (qfn12 package) 58 c/w junction to ambient ( ja ) (msop10 package) 128 c/w operating ambient temperature range -40 to 85 c storage temperature range -55 to 150 c esd rating - smclk, smdata, alert , therm pins - hbm 4000 v esd rating - all other pins - hbm 2000 v
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 11 revision 1.2 (09-27-10) datasheet 2.1 electrical specifications table 2.2 electrical specifications v dd = v bus = 3v to 24v, v pullup = 3v to 5.5v, t a = -40c to 85c, all typical values at v dd = v pullup = 3.3v, v bus = 12v, and t a = 27c unless otherwise noted. characteristic symbol min typ max unit conditions dc power supply voltage v dd 324v vdd pin supply current i dd 610 750 ua temp conversions at 0.0625 conversions / second, dynamic averaging disabled current sense active 650 950 ua temp conversions at 4 conversions / second, dynamic averaging disabled current sense active 950 1100 ua temp conversions at 8 conversions / second, dynamic averaging enabled current sense active vdd pin supply current i dd_ t_standby 750 ua temp conversions disabled (tmeas / stop = ?1?) current sense active vdd pin supply current i dd_all_ standby 300 ua temp conversions disabled (tmeas / stop = ?1?) current sense disabled (imeas / stop = ?1?) sense+ pin bias current i sense+ 90 ua v sense = 0v, v dd = 3v to 24v, current sense active 15 ua v sense = 0v, v dd = 3v to 24v, current sense disabled 10 20 ua v dd = 0v sense- pin bias current i sense- 10 ua v sense = 0v, v dd = 3v to 24v, current sense active 10 ua v sense = 0v, vdd = 3v to 24v, current sense disabled 0uav dd = 0v pull-up voltage v pullup 35.5v pull-up voltage for smbus, alert , and therm pins leakage current () i leak 5ua alert and therm pins, smdata and smclk pins powered or unpowered, t a < 85c
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 12 smsc EMC1701 datasheet current sense common mode voltage v cm 324v voltage on sense+ and/or sense- pins, referenced to ground differential mode voltage v diff -6 +6 v voltage between sense+ and sense- pins full scale range () (see section 5.16 ) fsr 0 10 mv 1 lsb = 4.885uv 0 20 mv 1 lsb = 9.77uv 0 40 mv 1 lsb = 19.54uv 0 80 mv 1 lsb = 39.08uv total measurement error () v sense _err 0.5 1 % total error, fsr = 80mv 3% total error, fsr = 10mv to 40mv offset error () v sense _off 3 lsb offset error, fsr = 80mv power supply rejection v sense _psr -120 db fsr = 10mv to 80mv, 3v < v dd < 24v common mode rejection v sense _cmr -110 db fsr = 10mv to 80mv, 3v < v bus < 24v source voltage full scale voltage fsv 3 23.9883 v voltage on sense+ pin total measurement error () (see section 4.1.2 ) v source _err 0.2 0.5 % power ratio full scale range 0 100 % 1 lsb = 1.53m% total measurement error () p ratio _err 1.6 % fsr = 80mv 3% fsr = 10mv to 40mv current sense peak detection peak detector threshold range v th 10 85 mv programmable via th_sel pin (EMC1701-1 only) peak detector duration range t dur 14096ms programmable via dur_sel pin (EMC1701-1 only) v sense peak detection t filter 5us table 2.2 electrical specifications (continued) v dd = v bus = 3v to 24v, v pullup = 3v to 5.5v, t a = -40c to 85c, all typical values at v dd = v pullup = 3.3v, v bus = 12v, and t a = 27c unless otherwise noted. characteristic symbol min typ max unit conditions
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 13 revision 1.2 (09-27-10) datasheet application note: the EMC1701 is trimmed at the 80mv range for best accuracy. 2.2 smbus electri cal specifications threshold accuracy () v th_err 25% v th = 80mv internal temperature monitor temperature accuracy () 0.25 1 c -5c < t a < 85c 2 c -40c < t a < 85c temperature resolution 0.125 c conversion times first conversion ready t conv_t 180 300 ms time after power up before temperature and voltage measurements updated and p ratio updated smbus delay t smb_d 25 ms time before smbus communications should be sent by host digital i/o pins (smclk, smdata, therm , alert ) input high voltage v ih 2.0 v smclk, smdata od pins pulled up to v pullup input low voltage v il 0.8 v output low voltage v ol 0.4 v od pin pulled to v pullup 4 ma current sink table 2.3 smbus elect rical specifications v dd = v bus = 3v to 24v, v pullup = 3v to 5.5v, t a = -40c to 85c typical values are at t a = 27c unless otherwise noted. characteristic symbol min typ max units conditions smbus interface input capacitance c in 410 pf smbus timing clock frequency f smb 10 400 khz spike suppression t sp 50 ns table 2.2 electrical specifications (continued) v dd = v bus = 3v to 24v, v pullup = 3v to 5.5v, t a = -40c to 85c, all typical values at v dd = v pullup = 3.3v, v bus = 12v, and t a = 27c unless otherwise noted. characteristic symbol min typ max unit conditions
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 14 smsc EMC1701 datasheet bus free time start to stop t buf 1.3 us setup time: start t su:sta 0.6 us setup time: stop t su:sto 0.6 us data hold time t hd:dat 0us data setup time t su:dat 0.6 us clock low period t low 1.3 us clock high period t high 0.6 us clock/data fall time t fall 300 ns min = 20+0.1c load ns clock/data rise time t rise 300 ns min = 20+0.1c load ns capacitive load c load 400 pf total per bus line table 2.3 smbus electrical specifications (continued) v dd = v bus = 3v to 24v, v pullup = 3v to 5.5v, t a = -40c to 85c typical values are at t a = 27c unless otherwise noted. characteristic symbol min typ max units conditions
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 15 revision 1.2 (09-27-10) datasheet chapter 3 communications 3.1 system management bus interface protocol the EMC1701 communicates with a host controller, su ch as an smsc sio, through the smbus. the smbus is a two-wire serial communication prot ocol between a computer host and its peripheral devices. a detailed timing diagram is shown in figure 3.1 . stretching of the smclk signal is supported; however, the EMC1701 will not stretch the clock signal. 3.1.1 smbus start bit the smbus start bit is defined as a transition of th e smbus data line from a logic ?1? state to a logic ?0? state while the smbus clock line is in a logic ?1? state. 3.1.2 smbus address and rd / wr bit the smbus address byte consists of the 7-bit client address followed by a 1-bit rd / wr indicator. if this rd / wr bit is a logic ?0?, the smbus host is writi ng data to the client device. if this rd / wr bit is a logic ?1?, the smbus host is re ading data from the client device. the EMC1701 smbus address is determined by a single resistor connected between ground and the addr_sel pin as shown in table 3.1 . figure 3.1 smbus timing diagram table 3.1 addr_sel resistor setting resistor (5%) smbus address resistor (5%) smbus address 0 1001_100(r/w) 1600 0101_000(r/w) 100 1001_101(r/w) 2000 0101_001(r/w) 180 1001_110(r/w) 2700 0101_010(r/w) 300 1001_111(r/w) 3600 0101_011(r/w) 430 1001_000(r/w) 5600 0101_100(r/w) smdata smclk t buf p s s - start condition p - stop condition p s t high t low t hd:sta t su:sto t hd:sta t hd:dat t su:dat t su:sta t fall t rise
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 16 smsc EMC1701 datasheet all smbus data bytes are sent most significant bit first and composed of 8-bits of information. 3.1.3 smbus ack and nack bits the smbus client will acknowledge all data bytes that it receives (as well as the client address if it matches and the ara address if the alert pin is asserted). this is done by the client device pulling the smbus data line low after the 8th bit of each byte that is transmitted. the host will nack (not acknowledge) the data re ceived from the client by holding the smbus data line high after the 8th data bit has been sent. 3.1.4 smbus stop bit the smbus stop bit is defined as a transition of the smbus data line from a logic ?0? state to a logic ?1? state while the smbus clock line is in a logic ?1? state. when the EMC1701 detects an smbus stop bit, and it has been communicating with the smbus pr otocol, it will reset its client interface and prepare to receive further communications. 3.1.5 smbus time-out the EMC1701 includes an smbus time -out feature. following a 30ms period of inactivity on the smbus, the device will time-out and reset the smbus interface. the time-out functionality defaults to disabled and can be enabled by writing to the timeout bit (see section 5.11 ). 3.1.6 smbus and i 2 c compliance the major differences between smbus and i 2 c devices are highlighted here. for complete compliance information, refer to the smbus 2.0 specification. 1. minimum frequency for smbus communications is 10khz. 2. the client protocol will reset if the clock is held at a logic ?0? for longer than 30ms. this time-out functionality is disabled by default. 3. the client protocol will reset if both the clock and data lines are held at a logic ?1? for longer than 150us. this function is disabled by default. 4. i 2 c devices do not support the alert response addre ss functionality (which is optional for smbus). 560 1001_001(r/w) 9100 0101_100(r/w) 750 1001_010(r/w) 20000 0101_101(r/w) 1270 1001_011(r/w) open 0011_000(r/w) table 3.1 addr_sel resistor setting (continued) resistor (5%) smbus address resistor (5%) smbus address
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 17 revision 1.2 (09-27-10) datasheet 3.2 smbus protocols the EMC1701 is smbus 2.0 compatible and supports send byte, read byte, receive byte, write byte, block read, and block write as valid protocols. it will respond to the alert response address protocol but is not in full compliance. all of the protocols listed below use the convention in ta b l e 3 . 2 . 3.2.1 write byte the write byte is used to write one byte of data to the registers, as shown in table 3.3 : 3.2.2 read byte the read byte protocol is used to read one byte of data from the registers, as shown in ta b l e 3 . 4 . 3.2.3 send byte the send byte protocol is used to set the internal address register pointer to the correct address location. no data is transferred during the send byte protocol, as shown in table 3.5 . table 3.2 protocol format data sent to device data sent to the host # of bits sent # of bits sent table 3.3 write byte protocol start slave address wr ack register address ack register data ack stop 1 -> 0 yyyy_yyy 0 0 xxh 0 xxh 0 0 -> 1 table 3.4 read byte protocol start slave address wr ack register address ack start slave address rd ack register data nack stop 1 -> 0 yyyy_yyy 0 0 xxh 0 0 -> 1 yyyy_yyy 1 0 xxh 1 0 -> 1 table 3.5 send byte protocol start slave address wr ack register address ack stop 1 -> 0 yyyy_yyy 0 0 xxh 0 0 -> 1
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 18 smsc EMC1701 datasheet 3.2.4 receive byte the receive byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via send byte). this is used for consecutive reads of the same register, as shown in table 3.6 . 3.2.5 block write the block write is used to write multiple data byte s to a group of contiguous registers, as shown in table 3.7 . it is an extension of the write byte protocol. 3.2.6 block read the block read is used to read multiple data bytes from a group of contiguous registers, as shown in table 3.8 . it is an extension of the read byte protocol. table 3.6 receive byte protocol start slave address rd ack register data nack stop 1 -> 0 yyyy_yyy 1 0 xxh 1 0 -> 1 table 3.7 block write protocol start slave address wr ack register address ack register data ack 1 ->0 yyyy_yyy 0 0 xxh 0 xxh 0 register data ack register data ack . . . register data ack stop xxh 0 xxh 0 . . . xxh 0 0 -> 1 table 3.8 block read protocol start slave address wr ack register address ack start slave address rd ack register data 1->0 yyyy_yyy 0 0 xxh 0 1 ->0 yyyy_yyy 1 0 xxh ack register data ack register data ack register data ack . . . register data nack stop 0 xxh 0 xxh 0 xxh 0 . . . xxh 1 0 -> 1
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 19 revision 1.2 (09-27-10) datasheet 3.2.7 alert response address the alert output can be used as a processor interr upt or as an smbus alert when configured to operate as an interrupt. when it detects that the alert pin is asserted, the host will send the alert response address (ara) to the general address of 0001_100xb. all devices with active interrupts will respond with their client address, as shown in ta b l e 3 . 9 . the EMC1701 will respond to the ara in the following way if the alert pin is asserted. 1. send slave address and verify that full slav e address was sent (i.e. the smbus communication from the device was not prematurely stopped due to a bus contention event). 2. set the mask bit to clear the alert pin. table 3.9 alert response address protocol start alert response address rd ack device address nack stop 1 -> 0 0001_100 1 0 yyyy_yyy 1 0 -> 1
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 20 smsc EMC1701 datasheet chapter 4 general description the EMC1701 is a combination high-side current sensing device with precision voltage and temperature measurement ca pabilities. it measures the voltage developed across an external sense resistor to represent the high-s ide current of a battery or voltage regulator. the EMC1701 also measures the source voltage and uses these m easured values to present a proportional power calculation. the EMC1701 contains additional bi-directional peak detection circuitry to flag instantaneous current spikes with programmable time duration and magnitude threshold. finally, the EMC1701 includes an internal diode channel for ambient temperature measurement. the EMC1701 current-sense measurement converts differential input voltage measured across an external sense resistor to a proportional output voltage. this voltage is digitized using a variable resolution (13-bit to 15-bit) sigma-delta adc and transmitted via the smbus or i 2 c protocol. the current range allows for large variations in meas ured current with high accuracy and low voltage drop across the resistor. the supply voltage is also measured and stored. when combined with the sense resistor voltage measurement the power provided from the source can be determined. programmable limits on both voltage and current levels are used to generate an interrupt. the EMC1701 has two levels of monitoring. the first provides a maskable alert signal to the host when the measured temperatures or voltages meet or exceed user programmable limits. this allows the EMC1701 to be used as an independent the rmal watchdog to warn the host of temperature hot spots without direct control by the host. the sec ond level of monitoring provides a non maskable interrupt on the therm pin if the measured values meet or exceed a second programmable limit. a system diagram is shown in figure 4.1 . figure 4.1 EMC1701 system diagram EMC1701 host smdata smclk alert dc load dc supply sense resistor therm vdd sense- sense+ 3.0v to 5.5v addr_sel th_sel** dur_sel** gnd vdd * * can either be dc supply voltage or a separate supply **EMC1701-1 only
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 21 revision 1.2 (09-27-10) datasheet 4.1 source monitoring the EMC1701 includes circuitry for both source current sensing and source voltage measurement. from these measurements, a ratiometric value co rresponding to the power delivered at the sense+ pin is provided. 4.1.1 current measurement the EMC1701 includes a high-side current sensing ci rcuit. this circuit measures the voltage, v sense , induced across a fixed external current sense resistor, r sense , and stores a representative voltage as a signed 11-bit number in the sense voltage registers (see section 5.18 ). this circuitry is able to measure the direction of current flow (from sense+ to sense- or from sense- to sense+). current flowing from sense+ to sense- is defined as positive current. current flowing from sense- to sense+ is defined as negative. the EMC1701 contains user programmable bipolar full scale sense ranges (fssr) of 10mv, 20mv, 40mv, or 80mv (see section 5.16 ). the default for this setting is 80mv. each v sense measurement is averaged over a user programmable time (see section 5.16 ). it is compared against programmable high and low limits (see section 5.21 ). if v sense exceeds (or drops below) the respective limits, the alert pin may be asserted (the default operation is to enable current sense interrupts on the alert pin). the EMC1701 also contains user programmable current peak detection circuitry (see section 4.1.4 ) that will assert the therm pin if a current spike is detected la rger than the programmed threshold and of longer duration than the programmed ti me. this circuitry is independent of v sense . full scale current (fsc) can be calculated from: actual source current through r sense can then be calculated using: for example: suppose the system is drawi ng 1.65a through a 10m resistor and the fsr is set for 20mv. therefore, by equation [1] , the fsc is 2a. for a positive voltage the sense voltage registers ar e read, ignoring the lower four bits since they are always zero, as 69_8h (0110_1001_1000b or 1688d) which is 82.5% of the full scale source current. this results in a calculated source current of 1.649a using equation [2] . where: [1] fsc is the full-scale current fsr, the full scale range, is either 10mv, 20mv, 40mv or 80mv (see section 5.16 ) r sense is the external sense resistor value where: [2] i source is the actual source current fsc is the full-scale current value (from equation [1] ) v sense is the value read from the sense voltage registers, ignoring the four lowest bits which are always zero (see section 5.18 ) fsc fsr r sense --------------------- = i source fsc v sense 2 047 , --------------------- =
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 22 smsc EMC1701 datasheet for a negative voltage the sense voltage registers are read as 96_8h, also ignoring the lower four bits since they are always zero. to calculate source current the binary value is first converted from two?s complement by inverting the bits and adding one: 96_8h = 1001_0110_1000b. inverting equals 0110_1001_0111b (69_7h) and adding one gives 0110_1001_1000b (69_8h). this results in the same calculated value as in the positive voltage case. 4.1.2 voltage measurement source voltage is measured on the supply side of the r sense resistor (sense+) and stored as an unsigned 11-bit number in the source voltage registers as v source (see section 5.19 ). each v source measurement is averaged over a user programmable time (see section 5.6 and section 5.15 ). the measurement is delayed by the programmed conversion rate. v source is compared against programmable high, low, and critical limits (see section 5.12 , section 5.13 , and section 5.14 ). if the value meets or exceeds the high limit s or drops below the low limits, the alert pin may be asserted (default is to enable this function ). if the value meets or exceeds the critical limit, the therm pin will be asserted (see section 5.23 ). full scale voltage (fsv) is given by the maxi mum value of the source voltage registers: actual source voltage at the sense+ pin can be calculated using: for example: suppose that the actual source voltage is 10.65v. the source voltage registers are read as v source = 71_ah (0111_0001_1010b or 1818d) which is 44.4% of the full scale source voltage. this results in a calculated source voltage of 10.65v using equation [4] . note that the actual source voltage may also be determined by scaling each bit set by the indicated bit weighting as described in section 5.19 . 4.1.3 power calculation the EMC1701 may be used to determine the average power provided at the source side of r sense (sense+) using the value, p ratio , contained in the power ratio registers (see section 5.20 ). the value represents the % of maximum calculable power. p ratio is mathematically generated by multiplying the absolute values of v sense and v source (see section 4.1.1 and section 4.1.2 ) and stored as a shifted 16-bit unsigned number. p ratio is updated whenever either v sense or v source is updated. where: [3] fsv is the full-scale voltage (a constant) where: [4] source voltage is the voltage at the sense+ pin fsv is the full-scale voltage (from equation [3] ) v source is the digital value read from the source voltage registers. note that the lowest five bits are always zero (see section 5.19 ) fsv 23.9883 v = source voltage fsv v source 4094 , ------------------------- - =
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 23 revision 1.2 (09-27-10) datasheet full scale power can be calculated from: actual power drawn from the source can be calculated using: for example: suppose that the actual source volt age is 10.65v and the source current through a 10m resistor is 1.65a. the fsc value is 2a per equation [1] ; thus, the expected power is 17.573w which is 36.6% of the fsp value. reading the power ratio registers will report p ratio as 24,003d (0101_1101_1100_0011b or 5d_c3h), which is 36.6% of the full scale source power. this results in a calculated source power of 17.6w. 4.1.4 current peak detection the EMC1701-1 includes a hardware set instantaneous current peak detector (this circuitry is also available in the EMC1701-2 but must be config ured via smbus). the peak detector threshold and duration values may also be set via the smbus. the peak detector supports detection of current spikes that occur faster than the minimum current sensing conversion time. this allows quick reacti on to events requiring system-level response. the circuitry compares the measured current against a us er-defined threshold value and user-defined time duration. if the measured current exceeds the threshold, an inter nal timer is started. if the timer reaches the programmed duration, the therm pin is asserted (see figure 4.2 for an example of peak current detectio n) and the peak status bit set. the therm pin will remain asserted until the peak is no longer detected at which point it will be released. the peak status bi t will likewise be cleared. the peak detection circuitry may also assert the alert pin. in this case, the alert pin must be configured to operate in comparator mode. if the alert pin is configured to operate in interrupt mode, the peak detection circuitry will not cause the alert pin to be asserted. the peak detection circuitry includes filtering (t filter ). when the instantaneous current exceeds the threshold, it must drop below the thresh old for a period of time greater than t filter before the timer is reset. the peak detection circuitry works for current flowing in either direction through the sense resistor (r sense ). application note: the peak detector circuitry works independently of the current meas urement integration. where: [5] fsp is the full-scale power fsc is the full-scale current (from equation [1] ) fsv is the full-scale voltage (from equation [3] ) where: [6] p source is the actual power provided by the source measured at sense+ fsp is the full-scale power (from equation [5] ) p ratio is the value read from the power ratio registers (see section 5.20 ) fsp fsc fsv = p source fsp p ratio 65 535 , ------------------- =
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 24 smsc EMC1701 datasheet the peak detector threshold is determined u pon device power up by the value of the resistor connected between the th_sel pin and ground (for EMC1701-1 only) or via the smbus (see section 5.17 ). the resistor selects one of 16 different v sense measurement limits (from 10mv to 85mv) as shown in ta b l e 4 . 1 . the peak detector duration is determined upon device power up by the value of the resistor between the dur_sel pin and ground (for em c1701-1 only) or via the smbus (see section 5.17 ). the resistor selects one of 16 different time duratio ns from 1 ms to 4.096s as shown in table 4.2 . figure 4.2 peak detection example table 4.1 th_sel resistor setting (EMC1701-1 only) resistor (5%) peak detection threshold resistor (5%) peak detection threshold 0 10mv 1600 50mv 100 15mv 2000 55mv 180 20mv 2700 60mv 300 25mv 3600 65mv 430 30mv 5600 70mv 560 35mv 9100 75mv 750 40mv 20000 80mv 1270 45mv open 85mv therm pin peak detector threshold t < t filter t > t filter t < t duration t > t duration t < t filter t > t filter
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 25 revision 1.2 (09-27-10) datasheet 4.2 vdd biasing options the wide device operating voltage range allows the EMC1701 to be powered from either the source voltage or an external supply. the EMC1701 contains circuitry to detect the voltage supply level on the vdd pin and enable an internal regulator as necessary. 4.3 modes of operation the EMC1701 has multiple modes of operation as described here: ? fully active - in this mode of operation, the dev ice is measuring the temperature channel, source voltage, and sense voltage. all data is updated at the end of the respective conversion and the limits are checked. writing to the on e-shot register will have no effect. ? current sense only - in this mode of operation, the device is measuring source voltage and sense voltage only. the temperature data is not updated. v source and v sense data are updated at the end of the respective conversion and the limits ar e checked. writing to the one-shot register will update the temperature measurements. this one-shot measurement may cause the alert or therm pins to be asserted if the measured te mperature violates the respective limits. ? temperature only - in this mode of operation, the device is measuring the temperature channels only. v source and v sense data are not updated. t he temperature data is updated at the end of the conversion and the limits are checked. wr iting to the one-shot register will update v source and v sense . this one-shot measurement may cause the alert or therm pins to be asserted if the measured voltage or current sense readin gs meet or exceed the respective limits. ? standby (stop) - in this mode of operation, the majority of circuitry is powered down to reduce supply current. the temperature, source vo ltage, and sense voltage measurements are not updated and the limits are not checked. in this mo de of operation, the smbus is fully active and the part will return requested data. writing to the one-shot register (see section 5.8 ) will enable the device to update all measurement channels (temperature, v source , and v sense ). this one- shot measurement may cause the alert or therm pins to be asserted if any of the measured values violate their respective limits. once all the channels are updated, the device will return to the standby mode. table 4.2 dur_sel resistor setting (EMC1701-1 only) resistor (5%) peak detection minimum duration (t duration )resistor (5%) peak detection minimum duration (t duration ) 0 1ms 1600 384ms 100 5ms 2000 512ms 180 26 ms 2700 768ms 300 51 ms 3600 1024ms 430 77 ms 5600 1536ms 560 102ms 9100 2048ms 750 128ms 20000 3072ms 1270 256ms open 4096ms
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 26 smsc EMC1701 datasheet 4.4 alert output the alert pin is an open drain output and requires a pull-up resistor to v pullup and has two modes of operation: interrupt mode and comp arator mode. the mode of the alert output is selected via the alert / comp bit in the configuration register (see section 5.5 ). the alert pin modes apply to the high limit only for all channels. the low limits will always cause the alert pin to behave as if it were in interrupt mode. the alert pin is used as an interrupt signal or as an smbus alert signal that allows an smbus slave to communicate an error condition to the master. one or more smbus alert outputs can be hard-wired together. 4.4.1 alert pin interrupt mode when configured to operate in interrupt mode, the alert pin asserts low when an out-of-limit measurement (> high limit or < low limit) is detected on any temperature measurement and the consecutive alert queue has been filled. additionally, the alert pin may be asserted if the measured current or the source voltage are out of limit (> high limit or < low limit). the alert pin will remain asserted as long as an out-of -limit condition remains. once the out-of-limit condition has been removed, the alert pin will remain asserted until the appropriate status bits are cleared. the pin can be masked by sett ing the mask_all bit. once the alert pin has been masked, it will be de-asserted and remain de-asserted until the mask_all bit is cleared by the user. any interrupt conditions that occur while the alert pin is masked will update the status register normally. when the alert pin is configured to operate in interrupt mode, the peak detector circuitry will not generate interrupts when a current peak is detected. 4.4.2 alert pin comparator mode when the alert pin is configured to operate in comparat or mode, it will be a sserted if the measured temperature meets or exceeds the high limit. the alert pin will remain asserted until the temperature drops below the high limit minus the tcrit hysteresis value (see section 5.9 ). additionally, the alert pin may be asserted if the measured current or the source voltage meet or exceed their respective high limit. the alert pin will remain asserted until the measured values drop below the corresponding high limit mi nus the vcrit hysteresis value (see section 5.23 ). when the alert pin is asserted in comparator mode, th e corresponding high limit status bits will be set. reading these bits will not clear them until the alert pin is deasserted. once the alert pin is deasserted, the status bits will be automatically cleared. the mask_all (see section 5.5 ) bit will not block the alert pin in this mode; however, individual mask bits (see section 5.10 ) will control the respective events that will assert the alert pin. when the alert pin is configured to operate in compar ator mode and the peak detector circuitry is linked to the alert pin, an interrupt will be generated when a current peak is detected (see section 5.15 ). 4.5 therm output the therm output is asserted independently of the alert output and cannot be masked. whenever the measured temperature meets or exceeds t he user programmed tcrit limit value for the programmed number of consecut ive measurements, the therm output is asserted. once it has been asserted, it will remain a sserted until the measured temperatures drops below the tcrit limit minus the tcrit hysteresis (also programmable). additionally, the therm pin will be asserted if the current sense peak detection circuitry has detected a current spike (see section 4.1.4 ). the therm pin will remain asserted so long as the peak detection circuitry continues to detect excessive instantaneous current (greater than the programmed threshold).
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 27 revision 1.2 (09-27-10) datasheet as well, the therm pin will be asserted if the measured curre nt or source voltage meet or exceed the user programmed vcrit limit va lues. in this case, the therm pin will remain asserted until all measured voltages drop below the vcrit limit minus the vcri t hysteresis (see section 5.23 ). 4.6 temperature measurement the EMC1701 measures the inter nal or ambient temperature. the device contains programmable high, low, and tcrit limits for the internal temperature channel. if the temperature drops below the low limit or meets or exceeds the high limit, the alert pin can be asserted (based on user settings). if the measured temperature meets or exceeds the tcrit limit, the therm pin is asserted unconditionally, provid ing two tiers of temperature detection.
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 28 smsc EMC1701 datasheet chapter 5 register description the registers shown in ta b l e 5 . 1 are accessible through the smbus. an entry of ?-? indicates that the bit is not used and will always read ?0?. table 5.1 register set in hexadecimal order register address r/w register name function default value page 00h r internal diode data high byte stores the integer data for the internal diode (mirrored at address 38h) 00h page 31 02h r status stores the status bits for the internal diode (mirrored at address 34h) 00h page 31 03h r/w configuration controls the general operation of the device (mirrored at address 09h) 00h page 32 04h r/w conversion rate controls the conversion rate for updating measurement data (mirrored at address 0ah) 06h (4/sec) page 33 05h r/w internal diode high limit stores the 8-bit high limit for the internal diode (mirrored at address 0bh) 55h (85c) page 33 06h r/w internal diode low limit stores the 8-bit low limit for the internal diode (mirrored at address 0ch) 80h (-128c) page 33 09h r/w configuration controls the general operation of the device (mirrored at address 03h) 00h page 32 0ah r/w conversion rate controls the conversion rate for updating measurement data (mirrored at address 04h) 06h (4/sec) page 33 0bh r/w internal diode high limit stores the 8-bit high limit for the internal diode (mirrored at address 05h) 55h (85c) page 33 0ch r/w internal diode low limit stores the 8-bit low limit for the internal diode (mirrored at address 06h) 80h (-128c) page 33 0fh w one-shot a write to this register initiates a one-shot update. 00h page 34 1fh r/w channel mask register controls the masking of individual channels 00h page 34 20h r/w internal diode tcrit limit stores the 8-bit critical temperature limit for the internal diode 64h (100c) page 34 21h r/w tcrit hysteresis stores the 8-bit hysteresis value that applies to all therm limits 0ah (10c) page 34
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 29 revision 1.2 (09-27-10) datasheet 22h r/w consecutive alert controls the number of out-of-limit conditions that must occur before an interrupt is asserted 70h page 35 29h r internal diode data low byte stores the fractional data for the internal diode (mirrored at register 39h) 00h page 31 34h r-c status stores the status bits for the measured temperature channels, current sense circuitry, and peak detector circuitry 00h page 31 35h r-c high limit status status bits for the high limits 00h page 36 36h r-c low limit status status bits for the low limits 00h page 36 37h r-c crit limit status status bits for the tcrit and vcrit limits 00h page 37 38h r internal diode high byte stores the integer data for the internal diode 00h page 31 39h r internal diode low byte stores the fractional data for the internal diode 00h page 31 current sense control and measurement 50h r/w voltage sampling configuration controls voltage sampling 80h page 37 51h r/w current sense sampling configuration controls the current sensing sampling and update times 03h page 38 52h r/w peak detection config controls the peak detection configuration 00h page 40 54h r sense voltage high byte stores the voltage measured across r sense 00h page 42 55h r sense voltage low byte 00h page 42 58h r source voltage high byte stores voltage measured on the source side of r sense 00h page 43 59h r source voltage low byte 00h page 43 5bh r power ratio high byte stores the power ratio value 00h page 43 5ch r power ratio low byte 00h page 43 current sense and source voltage limits 60h r/w sense voltage high limit stores the high limit for v sense 7fh page 44 table 5.1 register set in hexadecimal order (continued) register address r/w register name function default value page
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 30 smsc EMC1701 datasheet 5.1 data read interlock when any measurement channel high byte register is read (temperature or v source or v sense ), the corresponding low byte is copied into an internal ?shadow? register. the user is free to read the low byte at any time and be guaranteed that it will co rrespond to the previously read high byte. regardless if the low byte is read or not, r eading from the same high byte regist er again will automatically refresh this stored low byte data. 5.2 block mode support all of the status and temperature data may be retriev ed with a block read of 6 bytes starting at register address 34h. all of the voltage measurement, current sense da ta, and power information may be retrieved with a block read of 6 bytes starting at register address 54h. 61h r/w sense voltage low limit stores the low or negative limit for the v sense voltage 80h page 44 64h r/w source voltage high limit stores the high limit for the voltage on the source side of r sense ffh page 44 65h r/w source voltage low limit stores the low limit for the voltage on the source side of r sense 00h page 44 66h r/w sense voltage vcrit limit stores the critical limit for v sense 7fh page 44 68h r/w source voltage vcrit limit stores the critical limit for the voltage on the source side of r sense ffh page 44 69h r/w sense vcrit hysteresis stores the hysteresis for the v sense vcrit limit 0ah page 44 6ah r/w source voltage vcrit hysteresis stores the hysteresis for the source voltage vcrit limits 0ah page 44 fch r product features stores information about which pin controlled product features are set 00h page 45 fdh r product id stores a fixed value that identifies each product 38h page 45 feh r smsc id stores a fixed value that represents smsc 5dh page 46 ffh r revision stores a fixed value that represents the revision number 82h page 46 table 5.1 register set in hexadecimal order (continued) register address r/w register name function default value page
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 31 revision 1.2 (09-27-10) datasheet 5.3 temperature data registers as shown in table 5.2 , temperature data is stored as an 11-bit value with the high byte representing the integer value and the low byte representing the fr actional value left justified to occupy the msbits. 5.4 status register the status register reports general error condi tions. to identify specific channels, refer to section 5.12 , section 5.13 , and section 5.14 . the individual status register bits are cleared when the appropriate high limit, low limit, or crit li mit status register has been read or cleared. table 5.2 temperature data registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 00h r internal diode high byte sign 64 32 16 8 4 2 1 00h 38h 29h r internal diode low byte 0.5 0.25 0.125 - - - - - 00h 39h table 5.3 temperature data format temperature (c) binary hex (as read by registers) -63.875 1100_0000_001b c0_20h -63 1100_0001_000b c1_00h -1 1111_1111_000b ff_00h -0.125 1111_1111_111b ff_e0h 0 0000_0000_000b 00_00h 0.125 0000_0000_001b 00_20h 1 0000_0001_000b 01_00h 63 0011_1111_000b 3f_00h 64 0100_0000_000b 40_00h 65 0100_0001_000b 41_00h 127 0111_1111_000b 7f_00h 127.875 0111_1111_111b 7f_e0h table 5.4 status register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 02h r status busy peak - high low - crit - 00h 34h
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 32 smsc EMC1701 datasheet bit 7 - busy - this bit indicates that one of the adcs is currently converting. this bit does not cause either the alert or therm pins to be asserted. bit 6 - peak - this bit is set when the peak detect or circuitry has detected a current peak that is greater than the programmed threshold for longer th an the programmed duration. this bit is not sticky and will be cleared when the condition ha s been removed. when set, the therm pin or alert pin (comparator mode only) may be asserted (see section 5.15 ). bit 4 - high - this bit is set when any of the temperature channels meets or exceeds its programmed high limit. this bit will also be set if the v sense or v source channels meet or exceed their respective high limits. see the high limit status regi ster for specific channel information ( section 5.12 ). when set, the alert pin is asserted. bit 3 - low - this bit is set when any of the temperature channels drops below its programmed low limit. this bit will also be set if the v sense or v source channels drop below their respective low limits. see the low limit status register for specific channel information ( section 5.13 ). when set, the alert pin is asserted. bit 1 - crit - this bit is set when any of the temperature channels meets or exceeds its programmed tcrit limit. this bit will also be set if the v sense or v source channels meet or exceed their respective vcrit limits (see the section 5.14, "crit li mit status register" for specific channel information). when set, the therm pin is asserted. this bit is not sticky and will be cleared when the error condition has been removed. 5.5 configuration register the configuration register controls the basic operati on of the device. this register is fully accessible at either address. bit 7 - mask_all - masks the alert pin from asserting. ? ?0? (default) - the alert pin is not masked. if any of the appropriate status bits are set, the alert pin will be asserted. ? ?1? - the alert pin is masked if configured in interrupt mode (see section 4.4.1, "alert pin interrupt mode" ). the status registers will be updated normally. bit 6 - tmeas / stop - controls temperature measurement modes. ? ?0? (default) - the device is active , measuring the temperature channel. ? ?1? - the device is not measuring temperature c hannels. it will update the temperature channel when a one-shot command is given. bit 5 - alert/comp - controls the operation of the alert pin. ? ?0? (default) - the alert pin acts in interrupt mode as described in section 4.4.1 . ? ?1? - the alert pin acts in comparator mode as described in section 4.4.2 . in this mode the mask_all bit is ignored. bit 2 - imeas / stop - controls v sense and v source measurement modes. ? ?0? (default) - the device is measuri ng source voltage and sense voltage. table 5.5 configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 03h r/w configuration mask_ all tmeas /stop alert/ comp - - imeas /stop --00h 09h
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 33 revision 1.2 (09-27-10) datasheet ? ?1? -the device is not measuring the source voltage and sense voltage. it will update v sense and v source registers when a one-shot command is given. 5.6 conversion rate register the conversion rate register controls how often the v source and temperature measurement channels are updated and compared against the limits. this register is fully accessible at either address. bits 2-0 - t_conv[2:0] - determines the conversion rate as shown in ta b l e 5 . 7 . this conversion rate applies to temperature measurement and source voltage measurement. 5.7 temperature limit registers table 5.6 conversion rate register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 04h r/w conversion rate - - - - t_conv[2:0] 06h (4/sec) 0ah table 5.7 conversion rate t_conv[2:0] conversion rate 210 0 0 0 1 per 16 sec 0 0 1 1 per 8 sec 0 1 0 1 per 4 sec 0 1 1 1 per 2 sec 1 0 0 1 per sec 1 0 1 2 per sec 1 1 0 4 per sec (default) 1 1 1 8 per sec table 5.8 temperature limit registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 05h r/w internal diode high limit sign 64 32 16 8 4 2 1 55h (85c) 0bh 06h r/w internal diode low limit sign 64 32 16 8 4 2 1 80h (-128c) 0ch
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 34 smsc EMC1701 datasheet the device contains both high and low limits for the temperature channels. if the measured temperature meets or exceeds the high limit, the corresponding st atus bit is set, and the alert pin is asserted. likewise, if the measured temperature is less t han or equal to the low limit, the corresponding status bit is set and the alert pin is asserted. the limit registers with multiple addresses are fully accessible at either address. when the device is standby or curr ent sense only mode, updating the limit registers will have no effect until the next conversion cycle oc curs. this conversion cycle can be initiated vi a a write to the one- shot register or by clearin g the tmeas_stop bit in the c onfiguration r egister (see section 5.5 ). 5.8 one-shot register writing to the one-shot register will automati cally update those channel s that are not currently measured. if the device is fully active, writing to this register will have no effect. if the imeas_stop bit is set, writing to this register will update the v sense and v source voltage measurements. if the tmeas_stop bit is set, writing to this regist er will update all of the temperature channel measurements. 5.9 tcrit limit registers the tcrit limit registers are used to determine whet her a critical thermal event has occurred. if the measured temperature me ets or exceeds the tcrit limit, the therm pin is asserted. unlike the alert pin, the therm pin cannot be masked. additionally, the therm pin will be released once the temperature drops below the corresp onding threshold minus the tcrit hysteresis. 5.10 channel mask register table 5.9 one-shot register addr. r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 0fh w one-shot writing to this register initiates a si ngle conversion cycle. data is not stored and always reads 00h 00h table 5.10 tcrit limit registers addr. r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 20h r/w internal diode tc r i t l i m i t sign 64 32 16 8 4 2 1 64h (100c) 21h r/w tcrit hysteresis -643216 8 421 0ah (10c) table 5.11 channel mask register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 1fh r/w channel mask vsense_ mask vsrc_ mask peak_ mask - - - - int mask 00h
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 35 revision 1.2 (09-27-10) datasheet the channel mask register controls individual channel masking. when a channel is masked, the alert pin will not be asserted when the masked channel reads an out-of-limit error. the channel mask does not mask the therm pin. bit 7 - vsense_mask - masks the alert pin from asserting when the v sense value meets or exceeds the high limit or drops below the low limit. this bit will have no effect on the therm pin functionality. ? ?0? (default) - the v sense voltage channel will cause the alert pin to be asserted (if enabled). ? ?1? - the v sense voltage channel will not cause the alert pin to be asserted (if enabled). bit 6 - vsrc_mask - masks the alert pin from asserting when the v source value meets or exceeds the high limit or drops below the low limit. this bit will have no effect on the therm pin functionality. ? ?0? (default) - the v source voltage channel will cause the alert pin to be asserted (if enabled). ? ?1? - the v source voltage channel will not cause the alert pin to be asserted (if enabled). bit 5 - peak_mask - masks the alert pin from asserting when the peak detector circuitry detects a current spike. this bit will have no effect on the therm pin functionality. ? ?0? (default) - the peak detector circuitry will cause the alert pin to be asserted (if enabled). ? ?1? - the peak detector circuitry will not cause the alert pin to be asserted (if enabled). bit 0 - intmask - masks the alert pin from asserting when the internal diode temperature is out- of-limit. ? ?0? (default) - the internal diode channel will cause the alert pin to be asserted if it is out-of-limit. ? ?1? - the internal diode channel will not cause the alert pin to be asserted if it is out-of-limit. 5.11 consecutive alert register the consecutive alert register de termines how many times an out-o f-limit error must be detected in consecutive measurements before the interrupt status register s are asserted. this applies to temperature limits only. the vo ltage measurement and current sens e measurements are controlled via the voltage channel configuration register and curr ent sense configuration register respectively (see section 5.15 and section 5.16 ). when the alert pin is configured as a comparator, the co nsecutive alert counter will ignore low limit errors and only increment if the measured te mperature meets or exceeds the high limit. bit 7 - timeout - determines whether the smbus timeout function is enabled. ? ?0? (default) - the smbus timeout feature is disabled. the smclk line can be held low indefinitely without the device resetting its smbus protocol. ? ?1? - the smbus timeout feature is enabled. if the smclk line is held low for more than 30ms, the device will reset the smbus protocol. bits 6-4 - cthrm[2:0] - determines the number of consecutive measurements that must exceed the corresponding tcrit li mit before the therm pin is asserted. table 5.12 consecutive alert register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 22h r/w consecutive alert time out cthrm[2:0] calrt[2:0] - 70h
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 36 smsc EMC1701 datasheet bits 3-1 - calrt[2:0] - determine s the number of consec utive measurements that must have an out- of-limit condition before the alert pin is asserted. the bits are decoded as shown in ta b l e 5 . 1 3 . the default setting is 1 consecut ive out-of-limit conversion. 5.12 high limit status register the high limit status register contains the status bits that are set when a temperature or voltage channel high limit is met or exceeded. if any of t hese bits are set, the high status bit in the status register is set. reading from the high limit status register will clear all bits if the error condition has been removed. reading from the regi ster will also clear the high status bit in the status register if the error condition has been removed. if not masked, the alert pin will be set if the programmed num ber of consecutive alert counts have been met and any of these status bits are set. once set, the status bits will remain set until read unless the alert pin is configured as a comparator output (see section 4.4.2 ). bit 7 - vsense_high - this bit is set when the v sense value meets or exceeds its programmed high limit. bit 6 - vsrc_high - this bit is set when the v source value meets or exceeds its programmed high limit. bit 0 - ihigh - this bit is set when the internal diode channel meets or exceeds its programmed high limit. 5.13 low limit status register table 5.13 consecutive alert / therm settings 210 number of consecutive out-of-limit measurements 000 1 (default for calrt[2:0]) 001 2 011 3 111 4 (default for cthrm[2:0]) table 5.14 high limit status register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 35h r-c high limit status vsense_ high vsrc_ high - - - - - i high 00h table 5.15 low limit status register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 36h r-c low limit status vsense_ low vsrc_ low - - - - - ilow 00h
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 37 revision 1.2 (09-27-10) datasheet the low limit status register contains the status bits that are set when a temperature or voltage channel drops below the low limit. if any of these bits are set, the low status bit in the status register is set. reading from the low limit status register will clear all bits. reading from the register will also clear the low status bit in t he status register if the error status has been removed. if not masked, the alert pin will be set if the programmed num ber of consecutive alert counts have been met and any of these status bits are set. once set, the status bits will remain set until read. bit 7 - vsense_low - this bit is set when the v sense value drops below its programmed low limit. bit 6 - vsrc_low - this bit is set when the v source value drops below its programmed low limit. bit 0 - ilow - this bit is set when the internal diode channel drops below its programmed low limit. 5.14 crit limit status register the crit limit status register contains the status bits that are set when a temperature or voltage channel tcrit or vcrit limit is met or exceeded (see section 5.9 and section 5.23 ). if any of these bits are set, the crit status bit in the st atus register is set. reading from the crit limit status register will not clear the status bits. once t he temperature drops below the tcrit limit minus the tcrit hysteresis, the corresponding status bits will be automatically cl eared. once the voltage drops below the vcrit limit minus the vcrit hysteresis, the corresponding status bits will be automatically cleared. the crit bit in the status register will be cleared when all individual bits are cleared. bit 7 - vsense_vcrit - this bit is set when the v sense value meets or exceeds its programmed vcrit limit. when set, this bit will assert the therm pin. bit 6 - vsrc_vcrit- this bit is set when the v source value meets or exceeds its programmed vcrit limit. when set, this bit will assert the therm pin. bit 0 - itcrit - this bit is set when the internal diode channel meets or exceeds its programmed tcrit limit. when set, this bit will assert the therm pin. 5.15 voltage sampling configuration register the voltage sampling configuration register controls functionality for the source voltage measurement and peak detector circuitry. bit 7 - pk_alert_therm - de termines whether the alert pin or therm pin is asserted if the peak detector detects a current spike. if configured to assert the alert pin, the peak_mask can block the pin assertion normally. if configured to assert the therm pin, it will not be masked. table 5.16 crit limit status register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 37h r-c crit limit status vsense_ vcrit vsrc_ vcrit - - - - - itcrit 00h table 5.17 voltage sampling configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 50h r/w voltage sampling config pk_ alert_ therm - - - v_queue[1:0] v_avg[1:0] 80h
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 38 smsc EMC1701 datasheet ? ?0? - the peak detector circuitry will assert the alert pin when a current spike is detected. the alert pin must be configured to operate in comparator mode or it will not be asserted. ? ?1? (default) - the peak detector circuitry will assert the therm pin when a current spike is detected. bits 3 - 2 - v_queue[1:0] - determine the number of consecutive measurements that v source must exceed the limits before flagging an interrupt. bits 1-0 - v_avg[1:0] - controls the digital averaging that is applied to the source voltage measurement, as shown in ta b l e 5 . 1 9 . 5.16 current sense sampling configuration register the current sense sampling configuration register stores the controls for determining the current sense sampling / update time. bits 7 - 6 - cs_queue[1:0] - determine the numbe r of consecutive measurements that the measured v sense must exceed the limits before flagging an interrupt. table 5.18 voltage queue settings v_queue[1:0] number of consecutive ou t-of-limit measurements 10 0 0 1 (default) 01 2 10 3 11 4 table 5.19 voltage averaging settings v_avg[1:0] averaging 10 0 0 disabled (default) 012x 104x 118x table 5.20 current sense sampling configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 51h r/w current sense sampling config cs_queue [1:0] cs_samp_ avg [1:0] cs_samp_ time[1:0] cs_rng [1:0] 03h
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 39 revision 1.2 (09-27-10) datasheet bits 5 - 4 - cs_samp_avg[1:0] - determines t he number of averages t hat the current sensing circuitry will take as shown in ta b l e 5 . 2 2 . bits 3 - 2 - cs_samp_time[1:0] - determines the sa mpling time of the current sensing circuitry as shown in table 5.23 . the v sense voltage will be updated at this rate representing the average current over the sampling time multiplied by the averaging factor as shown in table 5.24 . table 5.21 sense queue settings cs_queue[1:0] number of consecutive ou t-of-limit measurements 10 0 0 1 (default) 01 2 10 3 11 4 table 5.22 current sense averaging settings cs_samp_avg[1:0] averaging 10 0 0 1x (default) 012x 104x 118x table 5.23 current sensing sampling time settings cs_samp_time[1:0] current sensor sampling time 10 0 0 82ms (default) 01 82ms 1 0 164ms 1 1 328ms
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 40 smsc EMC1701 datasheet bits 1 - 0 - cs_rng[1:0] - determines the current sense maximum expected voltage (full scale range) as shown in table 5.25 . 5.17 peak detection co nfiguration register the peak detection configuration register contro ls the threshold and durations used by the peak detection circuitry. at all times, the peak detection threshold and durat ion are set by the values written into this register. the resistors on the th_sel and dur_sel pins are used to determine the initial values of this register (EMC1701-1 only) and will not be retained if the value is over written by the user. these values may be updated at any time via the smbus. bits 7-4 - peak_det_th[3:0] - determines the pe ak detector threshold level as shown in ta b l e 5 . 2 7 . table 5.24 total sampling times sampling time averaging selection 1x 2x 4x 8x 82ms 82ms 164ms 328ms 655ms 164ms 164ms 328ms 655ms 1310ms 328ms 328ms 655ms 1310ms 2620ms table 5.25 current sensing range (full scale range) settings cs_rng[1:0] current sensor range 10 0 0 10mv 0 1 20mv 1 0 40mv 1 1 80mv (default) table 5.26 peak detection configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 52h r/w peak detection config peak_det_th[3:0] peak_det_dur[3:0] 00h
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 41 revision 1.2 (09-27-10) datasheet bits 4-0 - peak_det_dur[3:0] - determines the peak detector minimum time threshold as shown in table 5.28 . table 5.27 peak_det_ th[3:0] bit decode peak_det_th[3:0] peak detection threshold 3210 0 0 0 0 10mv 0 0 0 1 15mv 0 0 1 0 20mv 0 0 1 1 25mv 0 1 0 0 30mv 0 1 0 1 35mv 0 1 1 0 40mv 0 1 1 1 45mv 1 0 0 0 50mv 1 0 0 1 55mv 1 0 1 0 60mv 1 0 1 1 65mv 1 1 0 0 70mv 1 1 0 1 75mv 1 1 1 0 80mv 1 1 1 1 85mv table 5.28 peak_det_dur[3:0] bit decode peak_det_dur[3:0] peak detection minimum duration 3210 0000 1ms 0 0 0 1 5.12ms 0 0 1 0 25.6 ms 0 0 1 1 51.2 ms 0 1 0 0 76.8 ms 0 1 0 1 102.4ms 0 1 1 0 128.0ms 0 1 1 1 256.0ms
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 42 smsc EMC1701 datasheet 5.18 sense voltage registers the sense voltage regist ers store the measured v sense voltage across the sense resistor (r sense ) placed between the sense+ and sense- pins (see section 4.1.1, "current measurement" ). note that the bit weighting values are for repr esentation of the voltage relative to full scale. there is no internal scaling of data and all normal binary bit weightings still apply. the sense voltage register data format is standard 2?s complement format with the positive full scale value (7f_fh) and negative full scale value (80_0h) equal to the programmed maximum sense voltage (see section 5.16, "current sense sa mpling configuration register" ). the sign bit indicates the direction of current flow. if the sign bit is ?0?, current is flowing through r sense from the sense+ pin to the sense- pin. if the si gn bit is ?1?, the current is flowing through r sense from the sense- pin to the sense+ pin. see section 4.1.1, "current measurement" for examples. 1 0 0 0 384.0ms 1 0 0 1 512.0ms 1 0 1 0 768.0ms 1 0 1 1 1024.0ms 1 1 0 0 1536.0ms 1 1 0 1 2048.0ms 1 1 1 0 3072.0ms 1 1 1 1 4096.0ms table 5.29 sense voltage registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 54h r sense voltage high byte sign 1024 512 256 128 64 32 16 00h 55h r sense voltage low byte 8421 00h table 5.30 v sense data format v sense binary hex (as read by registers) minus full scale 1000_0000_0000 80_0h -2 lsb 1111_1111_1110 ff_eh -1 lsb 1111_1111_1111 ff_fh zero 0000_0000_0000 00_0h table 5.28 peak_det_dur[3:0] bit decode (continued) peak_det_dur[3:0] peak detection minimum duration 3210
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 43 revision 1.2 (09-27-10) datasheet 5.19 source voltage registers the source voltage registers store the voltage measured at the sense+ pin (see section 4.1.2, "voltage measurement" ) as a digital value, v source , consisting of a high byte and low byte with five of its lsbs always zero. the measured voltage is determined by summing the bit weights of each bit set. for example, if v bus was 7.4v, the source voltage registers would read 0100_1110 for the high byte and 1100_0000b for the low byte corresponding to 6v + 0.75v + 0.375v + 0.1875v + 0.046 9v + 0.0234v = 7.383v. the bit weightings are assigned for human interpreta tion. they should be disregarded when translating the information via a comp uting system as shown in section 4.1.2, "voltage measurement" . the source voltage registers cannot support ne gative values, and all values less than 0v will be recorded as 0v. 5.20 power ratio registers the power ratio registers store a power factor value that is used to determine the final average power delivered to the system (see section 4.1.3, "p ower calculation" ). the power factor value is the result of the multiplication of the v sense reading and the v source reading values shifted to a 16-bit number. it represents the ratio of delivered power with respect to maximum power. +1 lsb 0000_0000_0001 00_1h +2 lsb 0000_0000_0010 00_2h plus full scale 0111_1111_1111 7f_fh table 5.31 source voltage registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 58h r v source high byte 12 6 3 1.5 0.75 0.375 0.1875 0.0938 00h 59h r v source low byte 0.0469 0.0234 0.0117 - - - - - 00h table 5.32 power ratio registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 5bh r power ratio high byte 32768 16384 8192 4096 2048 1024 512 256 00h 5ch r power ratio low byte 128 64 32 16 8 4 2 1 00h table 5.30 v sense data format (continued) v sense binary hex (as read by registers)
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 44 smsc EMC1701 datasheet 5.21 v sense limit registers the v sense limit registers store a high and low limit for v sense . v sense is compared against both limits after each update. the data format for the limit is a raw binary form that is relative to the maximum v sense that has been programmed. if the measured sense voltage meets or exceeds the high limit or dr ops below the low limit, the alert pin is asserted and the vsense_hi gh or vsense_low status bits are set in the high limit status or low limit status registers (see section 5.12 and section 5.13 ). application note: v sense is always checked to be greater than the hi gh limit or less than the low limit including when v sense is negative. 5.22 source voltage limit registers the source voltage limit registers store the high and low limits for v source . v source is compared against all limits after each update. if v source meets or exceeds the corresponding high limit or drops below the low limit, the alert pin is asserted and the vsrc_high or vsrc_low status bits are set in the high limit status or low limit status registers (see section 5.12 and section 5.13 ). 5.23 critical voltage limit registers table 5.33 v sense limit registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 60h r/w sense voltage high limit sign 1024 512 256 128 64 32 16 7fh 61h r/w sense voltage low limit sign 1024 512 256 128 64 32 16 80h table 5.34 source volt age limit registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 64h r/w source voltage high limit 12 6 3 1.5 0.75 0.375 0.1875 0.0938 ffh 65h r/w source voltage low limit 12 6 3 1.5 0.75 0.375 0.1875 0.0938 00h table 5.35 critical vo ltage limit registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 66h r/w sense voltage vcrit limit sign 1024 512 256 128 64 32 16 7fh
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 45 revision 1.2 (09-27-10) datasheet the critical voltage limit regi sters store the critical voltage limits (vcrit limits) for v sense and v source . if the respective value meets or exceeds its critical limit, the therm pin will be asserted low and the respective vcrit status bit will be set (see section 5.14, "crit limit status register" ). it will remain asserted until the respective value drops below its li mit minus the respective vcrit hysteresis value. 5.24 product features regi ster (EMC1701-1 only) the product features register indicates functionality that is selected by the user based on pin states upon device power up. this register applies to the EMC1701-1 only. it will always read 00h for the EMC1701-2. bits 7-4 - th_sel[3:0] - indicates the selected peak detector threshold setting as determined by the th_sel pin. this value will be the default setti ng for the peak_det_th[3:0] bits and uses the same decode as given in ta b l e 5 . 2 7 . bits 3-0 - dur_sel[3:0] - indicates the select ed peak detector minimum duration setting as determined by the dur_sel pin. this value will be the default setting for the peak_det_dur[3:0] bits and uses the same decode as given in table 5.28 . 5.25 product id register the product id register holds a unique value that identifies the device. 68h r/w source voltage vcrit limit 12 6 3 1.5 0.75 0.375 0.1875 0.0938 ffh 69h r/w sense voltage vcrit hysteresis - - - 256 128 64 32 16 0ah 6ah r/w source voltage vcrit hysteresis - - - 1.5 0.75 0.375 0.1875 0.0938 0ah table 5.36 product features addrr/wregisterb7b6b5b4b3b2b1b0default fch r product features th_sel[3:0] dur_sel[3:0] 00h table 5.37 product id register addrr/wregisterb7b6b5b4b3b2b1b0default fdh r product id 00111000 38h table 5.35 critical voltage limit registers (continued) addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 46 smsc EMC1701 datasheet 5.26 smsc id register the manufacturer id register contains an 8-bit word that identifies smsc as the manufacturer of the EMC1701. 5.27 revision register the revision register contains an 8-bit word that identifies the die revision. table 5.38 manufacturer id register addr.r/wregisterb7b6b5b4b3b2b1b0default fehrsmsc id01011101 5dh table 5.39 revision register addr. r/w register b7 b6 b5 b4 b3 b2 b1 b0 default ffh r revision10000010 82h
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 47 revision 1.2 (09-27-10) datasheet chapter 6 package description 6.1 EMC1701-1 package drawin g (12-pin qfn 4mm x 4mm) figure 6.1 12-pin qfn 4mm x 4mm package drawings
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 48 smsc EMC1701 datasheet figure 6.2 12-pin qfn 4mm x 4mm package dimensions and notes figure 6.3 12-pin qfn 4mm x 4mm pcb footprint
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 49 revision 1.2 (09-27-10) datasheet 6.2 EMC1701-2 package dr awing (10-pin msop) note 6.1 although figure 6.1 the shows a picture of an 8-pin dev ice, dimensions are given for the 10-pin device in figure 6.2 . figure 6.1 10-pin msop package drawings (see note 6.1 )
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 50 smsc EMC1701 datasheet figure 6.2 10-pin msop package dimensions and notes
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 51 revision 1.2 (09-27-10) datasheet figure 6.3 10-pin msop pcb footprint
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 52 smsc EMC1701 datasheet 6.3 EMC1701 packa ge markings figure 6.1 EMC1701-1 package markings figure 6.2 EMC1701-2 package markings bottom bottom marking not allowed line: 1 ? smsc logo without circled (r) symbol line: 2 ? device id - version line: 3 ? last 7 digits of lot number line: 4 ? revision and country code (rcc) lines 1 to 3: center horizontal alignment line 4: left horizontal alignment pb-free/green symbol (matte sn) 0.41 3x 0.56 top e3 pin 1 1701 cc r 123456a - 1 e bottom line: 1-t ? device number line: 2-t version, revision, country code (vrcc) all top lines center horizontal alignment pb-free/green symbol (matte sn) 2x 1.5pt top e3 pin 1 line: 1-b ? date code (yyww) line: 2-b ? first 3 digits of lot number 3x 1.5pt pin 1 line: 3-b ? last 4 digits of lot number 17 01 2r cc yyww 123 456a
high-side current-sense and internal 1c temperature monitor datasheet smsc EMC1701 53 revision 1.2 (09-27-10) datasheet chapter 7 datasheet revision history table 7.1 customer revision history revision level & date secti on/figure/entr y correction rev. 1.2 (09-27-10) table 2.1, "absolute maximum ratings" added spec for voltage between sense pins. table 2.2, "electrical specifications" updated all electrical specs for current sense measurement, supply current, and peak detector. electrical specifications application note: added note: the EMC1701 is trimmed at the 80mv range for best accuracy. rev. 1.1 (06-16-10) system diagram updated. section 5.12, "high limit status register" and section 5.13, "low limit status register" alert# pin won?t be set if masked. table 5.25, "current sensing range (full scale range) settings" changed title from current sensing range to current sensing range (full scale range) settings. table 2.1, "absolute maximum ratings" upper limit of operating ambient temperature range changed from 125c to 85c. table 2.2, "electrical specifications" t a upper limit changed from 125c to 85c. bus voltage symbol changed from v source to v bus . i dd at 4 conversions/second with dynamic averaging enabled changed from 0.95 typ and 1.375 max to 0.9 typ and 1.3 max. i dd at 4 conversions/second with dynamic averaging disabled changed from 0.80 typ to 0.8 typ. i dd at 1 conversion/second with dynamic averaging disabled changed from 650 typ and 1 max to 0.7 typ and 1.0 max. v sense full scale sense range values changed from 0 min and +/- max values to - min values and + max values; conditions changed. total unadjusted v sense measurement error (v sense_tue ) renamed v sense measurement error (v sense_err ); typ value at 20-80mv fsr changed from 0.8 to +/-0.5 and max changed from +/-1.5 to +/-1; typ value at 10mv fsr changed from 0.2 to +/-0.8 and max changed from +/-2 to +/-1.5. v sense_off condition added. v sense measurement gain error has new symbol v sense_gn ; added typ +/-0.2 and changed max from 0.5 to +/-0.5. v th_err changed from +/-20 to +/-2. v source_err changed conditions; typ changed from 0.05 to +/-0.2 and max changed from 1 to +/- 0.5. added power ratio measurement specs. data hold time changed from 0.6 min and 6 max to 0 min and no max. section 5.27, "revision register" functional revision c changed default from 81h to 82h.
high-side current-sense and internal 1c temperature monitor datasheet revision 1.2 (09-27-10) 54 smsc EMC1701 datasheet document added EMC1701-2. rev. 1.0 (11-09-09) formal release table 7.1 customer revision history (continued) revision level & date secti on/figure/entr y correction

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